Lithography as a critical step for low-k dual damascene: from 248 nm to 193 nm

Author

Ronse, K. ; Maenhoudt, M. ; Pollentier, I. ; Wiaux, V. ; Struyf, H. ; Lepage, M. ; Vanhaelemeersch, S.

Author_Institution

IMEC, Leuven, Belgium

fYear

2000

fDate

2000

Firstpage

87

Lastpage

89

Abstract

Optical lithography is continuously pushed to its limits for volume manufacturing of integrated circuits. With the implementation of low-k dielectrics in the back-end-of-line processes, the optical properties of the dielectric stack have drastically changed. Also the transition from the conventional AlCu dry-etch scheme to several potential damascene integration schemes has significant impact on the lithography process and should be taken into account. Usually front-end-of-line development is considered as the driving force for lithography. However back-end lithography has become as challenging recently. In this paper, the various issues for back-end damascene lithography processes for the 0.13 um technology node will be outlined. The IMEC strategy for back-end-of-line lithography solutions will be outlined, for both 248 nm and 193 nm lithography

Keywords

copper; dielectric thin films; integrated circuit interconnections; sputter etching; ultraviolet lithography; 0.13 micron; 193 to 248 nm; Cu; DUV lithography; back-end-of-line processing; copper dual damascene interconnect; dry etching; integrated circuit manufacturing; low-k dielectric; process integration; Coatings; Damascene integration; Dielectric materials; Dry etching; Filling; Lithography; Optical control; Optical reflection; Planarization; Resists;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International

Conference_Location

Burlingame, CA

Print_ISBN

0-7803-6327-2

Type

conf

DOI

10.1109/IITC.2000.854290

Filename

854290