New strategy to improve the mechanical strength and to reduce potential contamination of dielectric materials for double level metal integration

Author

Assous, M. ; Morand, Y. ; Demolliens, O. ; Berruyer, P. ; Manierre, B. ; Gobil, Y. ; Louis, D. ; Feldis, H. ; Vizioz, C. ; Oman, A.F.

Author_Institution

CEA, Centre d´´Etudes Nucleaires de Grenoble, France

fYear

2000

fDate

2000

Firstpage

90

Lastpage

92

Abstract

This work concerns a new strategy for dual damascene Cu/low k integration in order to improve the mechanical strength and to reduce the contamination of the dielectric materials. We introduce the spacer concept in the dual damascene integration scheme with SiLK(R) dielectric. Two materials have been studied as spacers: SiN and TiN. The comparison is based on morphological aspects as well as electrical CD and Kelvin via resistance measurements for different strategies

Keywords

integrated circuit interconnections; mechanical strength; Kelvin via resistance; SiN; TiN; contamination; dielectric materials; double level metal integration; dual damascene Cu/low k integration; mechanical strength; Cleaning; Contamination; Copper; Dielectric materials; Etching; MOCVD; Plasma applications; Plasma chemistry; Silicon compounds; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International

Conference_Location

Burlingame, CA

Print_ISBN

0-7803-6327-2

Type

conf

DOI

10.1109/IITC.2000.854291

Filename

854291