Title :
LDMOS implementation by large tilt implant in 0.6 μm BCD5 process, flash memory compatible
Author :
Contiero, C. ; Galbiati, P. ; Palmieri, M. ; Vecchi, L.
Author_Institution :
Dedicated Products Group, SGS-Thomson Microelectron., Milan, Italy
Abstract :
This paper describes a method for integrating power LDMOS structures in a smart power Bipolar-CMOS-DMOS technology called BCD5 designed at 0.6 μm, compatible with VLSI EPROM, EEPROM and flash non volatile memories (NVM). The compatibility between NVM and LDMOS is achieved replacing conventional DMOS manufacturing processes, consisting of high temperature diffusion steps, with an innovative approach that exploits large angle of tilt implantation technique
Keywords :
BiCMOS integrated circuits; EPROM; VLSI; integrated circuit technology; ion implantation; power integrated circuits; 0.6 micron; BCD5 process; EEPROM; EPROM; LDMOS implementation; flash memory compatible; high temperature diffusion steps; large tilt implant; nonvolatile memories; power LDMOS structures; smart power bipolar-CMOS-DMOS technology; Application software; EPROM; Flash memory; Implants; Integrated circuit interconnections; Microelectronics; Nonvolatile memory; Silicon; Temperature; Very large scale integration;
Conference_Titel :
Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on
Conference_Location :
Maui, HI
Print_ISBN :
0-7803-3106-0
DOI :
10.1109/ISPSD.1996.509452
