• DocumentCode
    2192710
  • Title

    Optimal repeater insertion for n-tier multilevel interconnect architectures

  • Author

    Venkatesan, Raguraman ; Davis, Jeffrey A. ; Bowman, Keith A. ; Meindl, James D.

  • Author_Institution
    Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    132
  • Lastpage
    134
  • Abstract
    A new methodology to optimally insert repeaters for n-tier multilevel interconnect architectures is demonstrated. For a 0.1 μm ASIC macrocell case study, repeater insertion either decreases the macrocell area 4-fold (and lowers power dissipation by 50%), increases clock frequency by 22% or reduces number of metal levels by 25%
  • Keywords
    application specific integrated circuits; integrated circuit interconnections; repeaters; 0.1 micron; ASIC macrocell; N-tier multilevel interconnect architecture; optimal repeater insertion; Application specific integrated circuits; Clocks; Delay effects; Frequency; Inverters; Macrocell networks; Power dissipation; Repeaters; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
  • Conference_Location
    Burlingame, CA
  • Print_ISBN
    0-7803-6327-2
  • Type

    conf

  • DOI
    10.1109/IITC.2000.854303
  • Filename
    854303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2192710