Area-power efficient vedic multiplier using compressors

Vedic is famous for multiplication data representation. Vedic multiplier algorithm is used to improve the performance efficiency of the complex computations. In this paper, we proposed a novel 4:2 compressor and two 5:2 compressors architecture. In this architecture, we reduced latency and area. The performances of these compressors are evaluated by using Vedic algorithm. Proposed compressor architectures have shown better performance than existing Vedic algorithm based architecture.