Title :
The effectiveness of IDDQ and high voltage stress for burn-in elimination [CMOS production]
Author :
Kawahara, Rinya ; Nakayama, Osamu ; Kurasawa, Tatsuru
Author_Institution :
LSI Div., Kawasaki Steel Inc., Tochigi, Japan
Abstract :
IDDQ testing has been introduced to CMOS production lines for achieving higher quality and reliability. In addition, electrical stress applying method called High Voltage Stress (HVS) method was proposed for reliable rejection of weak insulation (such as gate oxide and interlayer separators). The capability of IDDQ testing and HVS method for elimination of burn-in process, an effective method to guarantee reliability but expensive, was investigated. The reduction of burn-in failure rate of 1.0 /spl mu/m product by introducing IDDQ testing prior to burn-in indicated that burn-in elimination was possible. Based on this result, burn-in elimination was accomplished for 0.5 /spl mu/m products followed by HVS method adoption. Failure analysis on IDDQ rejects of 0.5 /spl mu/m products have clarified IDDQ+HVS as alternative cost effective technology of conventional burn-in. Further investigation revealed that even IDDQ+HVS was not effective enough for screening devices made from badly contaminated wafers.
Keywords :
CMOS integrated circuits; failure analysis; integrated circuit manufacture; integrated circuit reliability; integrated circuit testing; production testing; quality control; 0.5 micron; 1 micron; CMOS production lines; HVS method; IDDQ testing; burn-in elimination; failure analysis; high voltage stress; reliability; CMOS technology; Circuit faults; Costs; Dielectrics and electrical insulation; Failure analysis; Large scale integration; Particle separators; Stress; Testing; Voltage;
Conference_Titel :
IDDQ Testing, 1996., IEEE International Workshop on
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-8186-7655-8
DOI :
10.1109/IDDQ.1996.557800
