DocumentCode
2192899
Title
0.42 μm contacted pitch dual damascene copper interconnect for 0.15 μm EDRAM using tapered via aligned to trench
Author
Hattori, Tsukasa ; Masuda, Hiroshi ; Sato, Haruhiko ; Matsuda, Takashi ; Yamamoto, Akihiro ; Kato, Yoshiaki ; Ogawa, Shinichi ; Ohsaki, Akihiko ; Ueda, Tetsuya
Author_Institution
ULSI Process Technol. Dev. Center, Matsushita Electron. Corp., Kyoto, Japan
fYear
2000
fDate
2000
Firstpage
155
Lastpage
157
Abstract
A tapered via aligned to a trench without any expanding of trench width for 0.42 μm contacted pitch dual damascene Cu interconnect has been studied. Cu via filling and via electrical properties were dependent on shapes of vias, and it has been found that the aligned tapered via has advantages for the fine pitch Cu dual damascene interconnect
Keywords
DRAM chips; copper; fine-pitch technology; integrated circuit interconnections; 0.42 micron; Cu; EDRAM; aligned tapered via; electrical properties; fine pitch dual damascene copper interconnect; trench; via filling; Capacitance; Contacts; Copper; Dielectric devices; Electric variables measurement; Fabrication; Filling; Shape; Sputtering; Ultra large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location
Burlingame, CA
Print_ISBN
0-7803-6327-2
Type
conf
DOI
10.1109/IITC.2000.854310
Filename
854310
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