Title :
Low leakage power designs of basic standard cells using gate-length biasing
Author :
Hu, Jianping ; Wang, Jun
Author_Institution :
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
Abstract :
In this paper, low leakage designs of several basic standard cells such as inverter, NAND and NOR are introduced into SMIC 130 nm CMOS libraries. The basic standard cells are optimized to achieve low leakage power delay product (PDP) using Gate-Length Biasing (GLB) technology. All circuits are simulated with HSPICE at a SMIC 130 nm CMOS technology and a 1.2 V supply voltage. The layout, abstract design and standard-cell characters of the standard cells are also described.
Keywords :
CMOS digital integrated circuits; NAND circuits; NOR circuits; delays; invertors; GLB technology; HSPICE simulation; NAND standard cell; NOR standard cell; SMIC CMOS technology; gate-length biasing technology; inverter standard cell; low leakage PDP; low leakage power delay product; size 130 nm; voltage 1.2 V; Adders; Delay; Inverters; Layout; Libraries; Logic gates; Power dissipation; gate-length biasing; integrafed circuits; low leakage design; standard cell;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6067618
