DocumentCode
2192939
Title
Delay analysis of wormhole based heterogeneous NoC
Author
Ben-Itzhak, Y. ; Cidon, Israel ; Kolodny, Avinoam
Author_Institution
Electr. Eng. Dept., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2011
fDate
1-4 May 2011
Firstpage
161
Lastpage
168
Abstract
We introduce a novel evaluation methodology to analyze the delay of a wormhole routing based NoC with variable link capacities and a variable number of virtual channels per link. This methodology can be utilized to analyze different heterogeneous NoC architectures and traffic scenarios for which no analysis framework has been developed before. In particular, it can replace computationally-extensive simulations at the inner-loop of the link capacities and virtual channels allocation steps of the NoC topology optimization process. Our analysis introduces a set of implicit equations which can be efficiently solved iteratively. We demonstrate the accuracy of our approximation by comparing the analysis results to a simulation model for several use-cases and synthetic examples. In addition, we compare the analysis with simulation results for a chip-multi-processor (CMP) using SPLASH-2 and PARSEC traces for both homogeneous and heterogeneous NoC configurations.
Keywords
microprocessor chips; multiprocessor interconnection networks; network routing; network-on-chip; NoC architectures; PARSEC traces; SPLASH-2 traces; chip-multiprocessor; delay analysis; networks-on-chip; topology optimization process; traffic scenarios; variable link capacities; variable number; wormhole based heterogeneous NoC; wormhole routing; Approximation methods; Delay; Analysis-Methodology; Delay Evaluation; Heterogeneous NoC; Networks-on-Chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
Conference_Location
Pittsburgh, PA
Electronic_ISBN
978-1-4503-0720-8
Type
conf
Filename
5948558
Link To Document