DocumentCode
2193255
Title
The XMOS XK-XMP-64 development board
Author
Hanlon, James
Author_Institution
XMOS Ltd., Bristol, UK
fYear
2011
fDate
1-4 May 2011
Firstpage
255
Lastpage
256
Abstract
The XMOS XK-XMP-64 is an experimental multi-processor board that demonstrates the scalability of the XS1 architecture; it connects 64 XCore processors, providing 512 hardware threads and 25.6 GIPS aggregate performance. This paper briefly overviews the XK-XMP-64, giving a simple example program and presenting the results of a set of experiments designed to benchmark its performance. These include message latencies and timings for barrier synchronisations and well-known static traffic permutations.
Keywords
distributed memory systems; multi-threading; parallel architectures; synchronisation; 64 XCore processor; GIPS aggregate performance; XMOS XK-XMP-64 development board; XS1 architecture; barrier synchronisation; distributed memory; hardware thread; message latency; multiprocessor board; static traffic permutation; Documentation; Hypercubes; Program processors; Programming; Scalability; Timing; XMOS; distributed-memory; multi-processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
Conference_Location
Pittsburgh, PA
Electronic_ISBN
978-1-4503-0720-8
Type
conf
Filename
5948572
Link To Document