Fabrication of SOI structures by uniform zone melting recrystallization for high voltage ICs

Author

Dilhac, J.-M. ; Zerrouk, D. ; Ganibal, C. ; Rossel, P. ; Bafleur, M.

Author_Institution

Lab. d´´Autom. et d´´Anal. des Syst., CNRS, Toulouse, France

fYear

1996

fDate

20-23 May 1996

Firstpage

215

Lastpage

218

Abstract

We present new experimental results about a method for creating thick silicon films on localized buried oxide layers, by superficial melting and solidification using a bank of tungsten halogen lamps. The purpose of this technique is to obtain cost-effective “partially SOI” substrates for high voltage smart power applications. Chemical defect revelation has been carried out in the SOI and seeded regions. N-channel MOSFETs have also been fabricated. It appears that crystallographic and electrical quality is sufficient for device processing

Keywords

MOS integrated circuits; integrated circuit technology; power MOSFET; power integrated circuits; silicon-on-insulator; zone melting; zone melting recrystallisation; HV smart power applications; N-channel MOSFET; NMOSFET; SOI structures; Si; W halogen lamps; fabrication process; high voltage IC; localized buried oxide layers; solidification; superficial melting; thick Si films; uniform zone melting recrystallization; Etching; Fabrication; Lamps; Rough surfaces; Semiconductor films; Silicon; Surface roughness; Temperature measurement; Thermal conductivity; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices and ICs, 1996. ISPSD '96 Proceedings., 8th International Symposium on

Conference_Location

Maui, HI

ISSN

1063-6854

Print_ISBN

0-7803-3106-0

Type

conf

DOI

10.1109/ISPSD.1996.509484

Filename

509484