A comprehensive Networks-on-Chip simulator for error control explorations

Author

Yu, Qiaoyan ; Zhang, Meilin ; Ampadu, Paul

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Rochester, Rochester, NY, USA

fYear

2011

fDate

1-4 May 2011

Firstpage

263

Lastpage

264

Abstract

Error control is imperative for reliable Networks-on-Chip (NoCs) design. In this demo session, we will present a CAD tool-a flexible and parallel NoC simulator. Our simulator evaluates the impact of different error control mechanisms on NoC performance and energy consumption in various noise and traffic injection scenarios. Our message passing interface language-based simulator can be executed on multiprocessors or server clusters. Multiple built-in blocks provide flexibility to evaluate different error control methods.

Keywords

CAD; application program interfaces; integrated circuit reliability; message passing; microprocessor chips; network-on-chip; CAD tool; NoC design reliability; comprehensive networks-on-chip simulator; energy consumption; error control explorations; message passing interface language-based simulator; multiprocessors; noise scenarios; parallel NoC simulator; server clusters; traffic injection scenarios; Benchmark testing; Design automation; Error correction; Servers; System-on-a-chip; Traffic control; Transient analysis; Networks-on-chip; PARSEC; fault tolerant; permanent error; simulator; transient error;

fLanguage

English

Publisher

ieee

Conference_Titel

Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on

Conference_Location

Pittsburgh, PA

Electronic_ISBN

978-1-4503-0720-8

Type

conf

Filename

5948577