DocumentCode
2193388
Title
NoCs simulation framework for OMNeT++
Author
Ben-Itzhak, Yaniv ; Zahavi, Eitan ; Cidon, Israel ; Kolodny, Avinoam
Author_Institution
Electr. Eng. Dept., Technion - Israel Inst. of Technol., Haifa, Israel
fYear
2011
fDate
1-4 May 2011
Firstpage
265
Lastpage
266
Abstract
As chip density keeps doubling every process generation, the use of Network-on-Chip becomes the prevalent architecture of SoC, MPSoC and large scale CMP designs. To that end, diverse NoC solutions are developed by the industry and the research community in order to meet heterogeneous on-chip communication requirements. Consequently, there is a growing need to rely on a simulation tools in order to explore, evaluate and optimize these new NoC architectures and topologies. The simulation platform is based on OMNeT++. It provides an open-source, modular, scalable, extendible and fully parameterizable framework for modeling NoC. In this demo we describe the structure of this framework.
Keywords
circuit simulation; network topology; network-on-chip; MPSoC; NoC architecture; NoC simulation; NoC topology; OMNeT++; chip density; heterogeneous on-chip communication; large scale CMP design; network-on-chip; open-source framework; Computational modeling; Computer architecture; Conferences; System-on-a-chip; Throughput; Topology; Traffic control; Networks-on-Chip; NoC Simulator;
fLanguage
English
Publisher
ieee
Conference_Titel
Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
Conference_Location
Pittsburgh, PA
Electronic_ISBN
978-1-4503-0720-8
Type
conf
Filename
5948578
Link To Document