• DocumentCode
    2193400
  • Title

    Spidergon STNoC design flow

  • Author

    Dubois, Florentine ; Cano, Jose ; Coppola, Marcello ; Flich, Jose ; Petrot, Frederic

  • Author_Institution
    TIMA Lab., UJF, Grenoble, France
  • fYear
    2011
  • fDate
    1-4 May 2011
  • Firstpage
    267
  • Lastpage
    268
  • Abstract
    In this demonstration we present an enhanced version of the usual Spidergon STNoC design flow. In addition, we show the automatic generation of a simulation platform that can be used to perform early architecture exploration.
  • Keywords
    logic design; logic simulation; network-on-chip; Spidergon STNoC design flow; automatic simulation platform generation; Analytical models; Computational modeling; Computer architecture; Design methodology; Mathematical model; Space exploration; System-on-a-chip; Architecture; Design flow; Design space exploration; Network on chips; Performance estimation; Spidergon STNoC; Synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
  • Conference_Location
    Pittsburgh, PA
  • Electronic_ISBN
    978-1-4503-0720-8
  • Type

    conf

  • Filename
    5948579
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2193400