DocumentCode :
2193458
Title :
A vertical bubble flow network using inductive-coupling for 3-D CMPs
Author :
Matsutani, Hiroki ; Take, Yasuhiro ; Sasaki, Daisuke ; Kimura, Masayuki ; Ono, Yuki ; Nishiyama, Yukinori ; Koibuchi, Michihiro ; Kuroda, Tadahiro ; Amano, Hideharu
Author_Institution :
Univ. of Tokyo, Tokyo, Japan
fYear :
2011
fDate :
1-4 May 2011
Firstpage :
49
Lastpage :
56
Abstract :
A wireless 3-D NoC architecture for CMPs, in which the number of processor and cache chips stacked in a package can be changed after the chip fabrication, is proposed by using the inductive coupling technology that can connect more than two known-good-dies without wire connections. Each chip has data transceivers for uplink and downlink in order to communicate with its neighboring chips in the package. These chips form a single vertical ring network so as to fully exploit the flexibility of the wireless approach that enables us to add, remove, and swap the chips in the ring. To avoid protocol and structural deadlocks in the ring network, we use the bubble flow control which is more flexible and efficient compared to the conventional VC-based deadlock avoidance. We implemented a real 3-D chip that has on-chip routers and inductive-coupling data transceivers using a 65nm process in order to show the feasibility of our proposal. The vertical bubble flow control is compared with the conventional VC-based approach and vertical bus in terms of the throughput, hardware amount, and application performance using a full system CMP simulator. The results show that the proposed vertical bubble flow network outperforms the VC-based approach by 7.9%-12.5% with a 33.5% smaller router area.
Keywords :
CMOS logic circuits; chip scale packaging; circuit simulation; integrated circuit interconnections; microprocessor chips; multiprocessor interconnection networks; network routing; network topology; network-on-chip; radio transceivers; three-dimensional integrated circuits; 3D CMP; bubble flow control; cache chips; chip fabrication; chip multiprocessors; data transceiver; full system CMP simulator; inductive coupling technology; integrated circuit packaging; multiprocessor interconnection; on-chip router; size 65 nm; three-dimensional network-on-chip; vertical bubble flow network; vertical ring network; wireless 3D NoC architecture; Computer architecture; Couplings; Downlink; System recovery; System-on-a-chip; Transceivers; Wireless communication; 3-D ICs; On-chip networks; inductive-coupling; many-core;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Networks on Chip (NoCS), 2011 Fifth IEEE/ACM International Symposium on
Conference_Location :
Pittsburgh, PA
Electronic_ISBN :
978-1-4503-0720-8
Type :
conf
Filename :
5948582
Link To Document :
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