• DocumentCode
    2193613
  • Title

    Dual logic and its application in logic minimization

  • Author

    Lunyao, Wang ; Yinshui, Xia ; Xiexiong, Chen

  • Author_Institution
    Fac. of Inf. Sci. & Eng., Ningbo Univ., Ningbo, China
  • fYear
    2011
  • fDate
    9-11 Sept. 2011
  • Firstpage
    239
  • Lastpage
    242
  • Abstract
    Based on the logic detection technique, a cover of a logic function is divided into two sections. One is for Boolean logic implementation and the other is for Reed-Muller logic implementation. Comparing to these minimization methods which using either Boolean logic or Reed-Muller logic only, the proposed method using dual logic produces less products. The proposed minimization method is implemented in C and tested on MCNC benchmarks.
  • Keywords
    Boolean algebra; minimisation of switching nets; Boolean logic implementation; MCNC benchmarks; Reed-Muller logic implementation; dual logic; logic detection technique; logic function; logic minimization; Algorithm design and analysis; Educational institutions; Logic functions; Minimization methods; Optimization; Programmable logic arrays; dual logic; logic decomposition; logic minimization; logic synthesis;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Communications and Control (ICECC), 2011 International Conference on
  • Conference_Location
    Ningbo
  • Print_ISBN
    978-1-4577-0320-1
  • Type

    conf

  • DOI
    10.1109/ICECC.2011.6067640
  • Filename
    6067640