Title :
Dual damascene architectures evaluation for the 0.18 μm technology and below
Author :
Vérove, C. ; Descouts, B. ; Gayet, P. ; Guillermet, M. ; Sabouret, E. ; Spinelli, P. ; van der Vegt, E.
Author_Institution :
STMicroelectron., Crolles, France
Abstract :
This paper compares three different schemes to pattern dual damascene (DD) structures. The Self Aligned (SA), Via First (VF), and Trench First (TF) architectures are compared in terms of complexity, process latitude, and sensitivity to lithography misalignment using 0.18-μm copper/oxide two metal level structures. The integration of thick metal lines is also discussed, for the upper levels of interconnects. This study shows that the VF architecture has the best via chain yield, regardless of the test configuration, and allows to pattern thick metal DD structures with high yield. The VF technique was used to manufacture a six copper level device, with functional yield similar to that obtained with an AlCu/HSQ Back End Of Line (BEOL)
Keywords :
copper; integrated circuit interconnections; 0.18 micron; Cu; copper multilevel interconnect; dual damascene structure; process integration; self-aligned architecture; trench first architecture; via first architecture; Copper; Costs; Etching; Lithography; Logic devices; Manufacturing; Robustness; Silicon compounds; Testing; Yield estimation;
Conference_Titel :
Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
Conference_Location :
Burlingame, CA
Print_ISBN :
0-7803-6327-2
DOI :
10.1109/IITC.2000.854344
