Title :
Simulated annealing based thermal-aware floorplanning
Author :
Qi, Lixia ; Xia, Yinshui ; Wang, Lunyao
Author_Institution :
Inst. of Circuits & Syst., Ningbo Univ., Ningbo, China
Abstract :
As technology advances, and the number of IP core in chips increases, power density in SoCs caused local temperature rose rapidly, which affects the stability of chips. Aiming at SoC thermal problem, combining to compact temperature model and application of effective cooling strategies, we propose a simulated annealing based thermal-aware floorplanning for SoC design. The proposed method is applied to MCNC benchmark circuits, the results show that the temperature for MCNC hp can be reduced up to 23°C.
Keywords :
circuit layout; cooling; integrated circuit design; simulated annealing; system-on-chip; IP core; SoC design; compact temperature model; effective cooling strategies; power density; simulated annealing; thermal-aware floorplanning; Benchmark testing; Cost function; Simulated annealing; Temperature distribution; Wires; Simulated Annealing; SoC; floorplanning; power density; thermal aware;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6067654
