RAPIDO: a modular, multi-board, heterogeneous multi-processor, PCI bus based prototyping framework for the validation of SoC VLSI designs

Author

Busá, Natalino ; Alkadi, Ghiath ; Verberne, M. ; Llopis, Rafael Peset ; Ramanathan, Sethuraman

Author_Institution

Philips Res. Lab., Eindhoven, Netherlands

fYear

2002

fDate

2002

Firstpage

159

Lastpage

165

Abstract

Modern System-on-Chip (SoC) designs are steadily increasing in complexity, while verification strategies, based on traditional logic simulations, are becoming extraordinarily and intolerably slow. On the other side, rapid system prototyping frameworks are not yet scalable and modular enough to prototype complex multi-processor systems. The proposed solution offers a modular approach for the validation of SoCs containing up to 128 heterogeneous processors. The RSP framework is based on a multi-board PCI architecture. An inter-task, layered data synchronization protocol has been implemented in order to ease HW-SW partitioning, co-design and design space exploration.

Keywords

VLSI; formal verification; hardware-software codesign; logic CAD; multiprocessing systems; peripheral interfaces; protocols; software prototyping; PCI bus; RAPIDO; SoC VLSI design validation; design space exploration; formal verification; hardware software codesign; hardware software partitioning; layered data synchronization protocol; logic simulations; multiboard heterogeneous multiprocessor; prototyping framework; rapid system prototyping; system-on-chip designs; Conferences; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Rapid System Prototyping, 2002. Proceedings. 13th IEEE International Workshop on

ISSN

1074-6005

Print_ISBN

0-7695-1703-X

Type

conf

DOI

10.1109/IWRSP.2002.1029752

Filename

1029752