DocumentCode :
2194108
Title :
A BIST-based solution for the diagnosis of embedded memories adopting image processing techniques
Author :
Appello, D. ; Fudoli, A. ; Tancorre, V. ; Corno, F. ; Rebaudengo, M. ; Reorda, M. Sonza
Author_Institution :
STMicroelectronics, Cornaredo, Italy
fYear :
2002
fDate :
2002
Firstpage :
12
Lastpage :
16
Abstract :
This paper proposes a new solution for the diagnosis of faults in embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuitry added to the BIST selecting the failure data, and the ATE test program to schedule the data extraction flow. Testing is possible through a standard IEEE 1149.1 TAP, and allows the access to multiple cores with a P1500 compliant solution. The approach aims at implementing a low-cost solution to diagnose embedded RAMs with the goal of minimizing the ATE costs and the time required to extract the diagnostic information. In our approach, the ATE drives the diagnostic scheme and is dedicated to the classification of faults, only, allowing adopting low-cost equipment. The proposed solution allows a scalable extraction of test data, whose amount is proportional to the available testing time. In order to accelerate the fault classification, image processing techniques have been applied The Hough transform has been adopted to analyze the bitmap representing the faulty cells. Preliminary experimental results show the advantages of the proposed approach in terms of time required to complete a diagnostic process.
Keywords :
Hough transforms; automatic testing; built-in self test; fault diagnosis; image classification; integrated circuit testing; integrated memory circuits; logic testing; random-access storage; ATE test program; BIST; BIST-based solution; Hough transform; P1500 compliant solution; STMicroelectronics; data extraction flow scheduling; dedicated circuitry; diagnostic process; embedded RAMs; embedded memories; failure data; fault classification; faulty cells bitmap analysis; image processing techniques; multiple cores; scalable test data extraction; standard IEEE 1149.1 TAP; Acceleration; Built-in self-test; Circuit faults; Circuit testing; Costs; Data mining; Fault diagnosis; Image analysis; Image processing; Random access memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
ISSN :
1087-4852
Print_ISBN :
0-7695-1617-3
Type :
conf
DOI :
10.1109/MTDT.2002.1029757
Filename :
1029757
Link To Document :
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