Title :
A scan-BIST environment for testing embedded memories
Author :
Karimi, F. ; Lombardi, F.
Author_Institution :
LTX Corp., San Jose, CA, USA
Abstract :
This paper presents a new IEEE 1149.1 compatible architecture as an intermediate environment for testing embedded memories. A BIST structure and a boundary scan are used for testing various memory configurations for programmability as well as improved controllability and observability. Its novelty is that features such as modularity, scalability with word size and adaptability to different memory configurations and testing requirements, are accomplished at relative ease. In the boundary scan, user-defined test modes are utilized so that basic modifications to the elements of a seed algorithm can be generated very efficiently.
Keywords :
boundary scan testing; built-in self test; controllability; integrated circuit testing; integrated memory circuits; logic testing; observability; BIST structure; IEEE 1149.1 compatible architecture; boundary scan; controllability; embedded memory testing; fully customized march element; intermediate environment; modularity; observability; programmability; scalability; scan-BIST environment; user-defined test modes; Automatic testing; Built-in self-test; Computer architecture; Controllability; Embedded computing; Hardware; Observability; SRAM chips; Scalability; System-on-a-chip;
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
Print_ISBN :
0-7695-1617-3
DOI :
10.1109/MTDT.2002.1029758
