FPGA implementation of network on chip based on Pentacle topology

A novel topology based on pentacle is proposed for network on chip (NoC). Johnson coding and global asynchronous local synchronous (GALS) are applied to improve the performance of NoC and the resource utilization of FPGA. Simulation results show that, compared with 2D Mesh and Octagon, Pentacle achieves average latency reductions of 30.7% and 15.0%, and increases throughput of 17.6% and 8.1%, respectively. Pentacle topology, which focuses on reducing latency and increasing throughput, is validated by simulation and implemented on FPGA.