Title :
Adder merged DRAM architecture
Author :
Hashimoto, Masashi
Author_Institution :
Cadence Design Syst., Japan
Abstract :
A 4-level sensing scheme utilizing base-4 operation addition and subtraction executable DRAM array has been developed. Neither DRAM functions, performance, nor silicon area will be sacrificed by implementing the circuit. Addition/subtraction will be executed using the massively parallel SIMD, resulting in a high degree of concurrency. Performance of around 50GOPS performance can be achieved in the case where the adder is implemented into 64 Mb DRAM array.
Keywords :
DRAM chips; adders; cellular arrays; memory architecture; parallel architectures; 64 Mbit; adder merged DRAM architecture; base-4 operation addition; base-4 operation subtraction; concurrency; executable DRAM array; four-level sensing scheme; massively parallel SIMD; silicon area; Adders; Concurrent computing; Digital circuits; MOSFETs; Operational amplifiers; Random access memory; Registers; Silicon; Tin; Voltage;
Conference_Titel :
Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
Print_ISBN :
0-7695-1617-3
DOI :
10.1109/MTDT.2002.1029768
