DocumentCode
2194403
Title
A parallel, high-performance bus interconnection scheme
Author
Li, Kang ; Fan, Yong ; Zhao, Qing-He ; Hao, Yue
Author_Institution
Dept. Microelectron., Xidian Univ., Xi´´an, China
fYear
2011
fDate
9-11 Sept. 2011
Firstpage
90
Lastpage
92
Abstract
This paper present a parallel, split bus interconnection scheme for the multi-processor system. The scheme provides a command bus and a set of data bus, each of which works independently. This bus interconnect scheme can greatly improve the bandwidth of data communication within the multi-processor system because of its characteristics of concurrency and separability.
Keywords
multiprocessing systems; parallel processing; system buses; command bus; concurrency characteristics; data bus; multiprocessor system; parallel high-performance split bus interconnection scheme; separability characteristics; Bandwidth; Data communication; Data processing; Integrated circuit interconnections; Random access memory; Registers; Throughput; bus arbiter; bus interconnection; multi-processor;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location
Ningbo
Print_ISBN
978-1-4577-0320-1
Type
conf
DOI
10.1109/ICECC.2011.6067672
Filename
6067672
Link To Document