Title :
A design of the PLB to AHB bus bridge
Author :
Li, Kang ; Lei, Li ; Fan, Yong ; Shi, Jiang-Yi ; Hao, Yue
Author_Institution :
Dept. Microelectron., Xidian Univ., Xi´´an, China
Abstract :
The study in this paper is to solve the compatibility of the PLB and AHB interface. In our FPGA hardware platform, we use the PowerPC embedded in Xilinx Virtex4 as our CPU, which follows the PLB protocol. As our slave IP cores are all designed with the AHB interface, we need to design a PLB-AHB bridge to translate the two protocols. This paper describes in detail the designing of such a bridge, which enables the use of AHB interface IP cores in our PLB bus environment.
Keywords :
field programmable gate arrays; peripheral interfaces; AHB bus bridge; AHB interface IP cores; CPU; FPGA hardware platform; PowerPC embedded; Xilinx Virtex4; Bridges; Clocks; Data communication; Program processors; Protocols; System-on-a-chip; Timing; AHB; FPGA prototyping; PLB; bridge; timing conversion;
Conference_Titel :
Electronics, Communications and Control (ICECC), 2011 International Conference on
Conference_Location :
Ningbo
Print_ISBN :
978-1-4577-0320-1
DOI :
10.1109/ICECC.2011.6067676
