DocumentCode :
2194601
Title :
Efficient worst case timing analysis of data caching
Author :
Kim, Sung-Kwan ; Min, Sang Lyul ; Ha, Rhan
Author_Institution :
Dept. of Comput. Eng., Seoul Nat. Univ., South Korea
fYear :
1996
fDate :
10-12 Jun 1996
Firstpage :
230
Lastpage :
240
Abstract :
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching. However there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). The paper proposes two techniques to minimize the WCET overestimation due to such load/store instructions. The first technique uses a global data flow analysis technique to reduce the number of load/store instructions that are misclassified as dynamic load/store instructions. The second technique utilizes data dependence analysis to minimize the adverse impact of dynamic load/store instructions. The paper also compares the WCET bounds of simple benchmark programs that are predicted with and without applying the proposed techniques. The results show that they significantly (up to 20%) improve the accuracy of WCET estimation especially for programs with a large number of references from dynamic load/store instructions
Keywords :
cache storage; computational complexity; instruction sets; real-time systems; reduced instruction set computing; WCET overestimation; accurate timing analysis; benchmark programs; cache block; data caching; data dependence analysis; dynamic load/store instructions; efficient worst case timing analysis; global data flow analysis; multiple memory locations; pipelined execution; pointer based references; Computer aided instruction; Computer aided software engineering; Computer languages; Data analysis; Dynamic programming; Processor scheduling; Real time systems; Reduced instruction set computing; Scheduling algorithm; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Real-Time Technology and Applications Symposium, 1996. Proceedings., 1996 IEEE
Conference_Location :
Brookline, MA
Print_ISBN :
0-8186-7448-2
Type :
conf
DOI :
10.1109/RTTAS.1996.509540
Filename :
509540
Link To Document :
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