• DocumentCode
    2194658
  • Title

    Decreasing EEPROM programming bias with negative voltage, reliability impact

  • Author

    Laffont, R. ; Razafindramora, J. ; Canet, P. ; Bouchakour, R. ; Mirabel, J.M.

  • Author_Institution
    L2MP/Polytech, CNRS, Marseille, France
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    168
  • Lastpage
    173
  • Abstract
    This paper presents a study of EEPROM cell programming in order to decrease the bias polarization of the memory cell. Simulations show that it is possible to erase and write a cell with a divide up polarization, with positive and negative pulses. Measurements on a memory cell confirm these statements. Moreover simulations of the electrical field through the tunnel oxide didn´t show any change of the maximum value, that means there is no impact on cell reliability. Endurance tests were performed on several memory cells with divide up polarizations. They show the same results as classical programming.
  • Keywords
    EPROM; PLD programming; cellular arrays; integrated circuit reliability; life testing; EEPROM programming bias; bias polarization; cell programming; divide up polarizations; electrical field; endurance tests; negative pulses; positive pulses; reliability; tunnel oxide; Application specific integrated circuits; Capacitance; EPROM; Independent component analysis; Nonvolatile memory; Polarization; Programmable logic devices; Rain; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design and Testing, 2002. (MTDT 2002). Proceedings of the 2002 IEEE International Workshop on
  • ISSN
    1087-4852
  • Print_ISBN
    0-7695-1617-3
  • Type

    conf

  • DOI
    10.1109/MTDT.2002.1029781
  • Filename
    1029781