DocumentCode
2194813
Title
Vector instruction set support for conditional operations
Author
Smith, J.E. ; Faanes, Greg ; Sugumar, Rabin
Author_Institution
Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
fYear
2000
fDate
14-14 June 2000
Firstpage
260
Lastpage
269
Abstract
Vector instruction sets are receiving renewed interest because of their applicability to multimedia. Current multimedia instruction sets use short vectors with SIMD implementations, but long vector, pipelined implementations have a number of advantages and are a logical next step in multimedia ISA development. Support for conditional operations (as occur in loops containing IF statements) is an important aspect of a vector ISA. Seven ISA alternatives for implementing conditional operations are systematically explored. Performance considerations are discussed through evaluation of a typical IF loop over a range of vector lengths and true conditional values. An approach using masked operations is shown to be one of the better methods, especially if its implementation is able to skip over blocks of false mask bits. Additional analyses of complex IF loops and parallel pipeline implementations support the masked operation approach. The paper concludes with a practical implementation of masked operations that skips over power-of-2-length blocks of false values. This implementation is simpler than skipping arbitrary-length blocks and provides similar performance.
Keywords
instruction sets; parallel architectures; performance evaluation; vector processor systems; conditional operations; multimedia ISA development; multimedia instruction sets; performance considerations; vector instruction set support;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 2000. Proceedings of the 27th International Symposium on
Conference_Location
Vancouver, BC, Canada
ISSN
1063-6897
Print_ISBN
1-58113-232-8
Type
conf
Filename
854396
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