Low power high speed VLSI architecture for 1-D Discrete wavelet transform

This paper presents an implementation of 1-D Discrete wavelet transform DWT using systolic array architecture. It performs calculations of low pass and high pass coefficients by using only one multiplier. This architecture has been implemented and simulated using VLSI. The systolic nature of this architecture corresponds to a clock speed of 19.27MHz for Coiflets1 wavelet and low power of 88.9mW for Haar wavelet. It has advantage for optimizing area and time. The architecture is modular and cascadable for one or multi-dimensional DWT.