DocumentCode :
2195877
Title :
Pipelined FFT architectures: A review
Author :
Singh, Sharad ; Kedia, Jyoti
Author_Institution :
Electronics and communication Engg. dept., PEC university of Technology, 160012, India
fYear :
2015
fDate :
24-25 Jan. 2015
Firstpage :
1
Lastpage :
5
Abstract :
The Fast Fourier Transform processing is one of the key procedure in popular Orthogonal frequency Division Multiplexing (OFDM). FFT processor is the most computationally intensive component in OFDM systems[1]. The power efficiency of this component can have great impact on overall OFDM systems. The low power consumption, high speed and reduced chip area are the main concerns in VLSI implementation. In view of that this paper explores various pipeline FFT Processor architectures that aim to reduce the power consumption of these devices.
Keywords :
Delays; Memory management; OFDM; Pipelines; Switches; Very large scale integration; FFT; IFFT; OFDM; RADIX;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location :
Visakhapatnam, India
Print_ISBN :
978-1-4799-7676-8
Type :
conf
DOI :
10.1109/EESCO.2015.7253865
Filename :
7253865
Link To Document :
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