Novel Energy Efficient one bit Full Subtractor at 65nm technology

In this work one bit Full Subtractor with Twenty and Fourteen transistors have been proposed. Reducing Power dissipation, supply voltage, leakage currents, area of chip are the most important parameters in today´s VLSI designs. The system reliability can be increased by reducing the cost, weight and physical size and it is achieved by decreasing the transistor count. Therefore the minimum power consumption target and lower area can be meet by reducing the hardware size. Digital circuits can be minimize in two methods. One is human method and another is Computational method. This paper propose one-bit Full Subtractor based on human method with twenty and fourteen transistors and simulation for the designed circuits were also performed with MTCMOS technique. Finally the simulation analysis were compared with conventional Full Subtractor in terms of total power consumption, delay, area and power delay product.