Title :
The impact of gate and channel length of a Si LDMOS transistor on its on resistance and breakdown voltage
Author :
Chahar, Suman ; Rather, G.M.
Author_Institution :
Department of Electronics and Communication, National Institute of Technology, Srinagar, Jammu & Kashmir 190006, India
Abstract :
In this paper, the electrical characteristics of LDMOS transistor has been analyzed through simulations. The parameters of LDMOS namely breakdown voltage (BV) and on resistance, with variation in gate and channel length have been studied. This paper presents a distinct model of lateral double diffused MOS (LDMOS) transistor having small size with different characteristics. This investigation revealed some improved on resistance and breakdown voltage of the device.
Keywords :
Doping; Immune system; Logic gates; Mathematical model; Resistance; Semiconductor process modeling; Transistors; Breakdown Voltage; LDMOS; On Resistance;
Conference_Titel :
Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 International Conference on
Conference_Location :
Visakhapatnam, India
Print_ISBN :
978-1-4799-7676-8
DOI :
10.1109/EESCO.2015.7253874
