Continuous-Time/Discrete-Time (CT/DT) Cascaded Sigma-Delta Modulator for High Resolution and Wideband Applications

This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18 ¿m CMOS technology and achieves 84 dB dynamic range for a 10 MHz signal bandwidth. Total analog power dissipation measured was 44 mW.