• DocumentCode
    2196266
  • Title

    All Digital Multiplying DLL Using Precision Digital Delay Line as DCO

  • Author

    Lee, Seong-Hoon

  • Author_Institution
    Micron Technol. Inc., Boise, ID, USA
  • fYear
    2010
  • fDate
    16-16 April 2010
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    In this paper all digital multiplying delay-locked loop (MDLL) is presented, which uses a 3rd order precision digital delay line (HDL) as DCO. Maximum locking frequency at 1.3 V was 1 GHz with multiplication factor of 50, assuming 20 MHz reference clock frequency, and peak to peak jitter was ± 61617; 20ps. DCO consumed only 2.2 mW, and the rest logic 3.5 mW.
  • Keywords
    delay lines; delay lock loops; multiplying circuits; all digital multiplying DLL; delay-locked loop; phase mixer; power 2.2 mW; power 3.5 mW; precision digital delay line; voltage 1.3 V; Clocks; Delay effects; Delay lines; Frequency; Hardware design languages; Jitter; Logic gates; Phase locked loops; Robust stability; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microelectronics and Electron Devices (WMED), 2010 IEEE Workshop on
  • Conference_Location
    Boise, ID
  • ISSN
    1947-3842
  • Print_ISBN
    978-1-4244-6572-9
  • Type

    conf

  • DOI
    10.1109/WMED.2010.5453774
  • Filename
    5453774
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2196266