A design of video capture-output and pre-processing system based on FPGA

Author

Chunping, Wang ; Xijun, Gao ; Qiang, Fu

Author_Institution

Dept. of Opt. & Electron. Eng., Ordnance Eng. Coll. PLA, Shijiazhuang, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

21

Lastpage

24

Abstract

A FPGA-based video capture, output and pre-treatment system has been developed. The system adopts the I²C bus protocol and link-port data transfer protocol. And also it combines PAL video format to complete the process of video-capture, decode, encording and output. With the help of IP core provided by Altera company, it achieves the DDR controller, providing storage space for video images. Median filtering algorithm is used to achieve video pre-processing. Experimental verification, real-time acquisition video image of 25 frames/s can be displayed by system, and it completes better pre-processing algorithm to achieve purposes of noise reduction.

Keywords

field programmable gate arrays; median filters; microprocessor chips; protocols; video coding; Altera company; DDR controller; FPGA; I²C bus protocol; IP core; PAL video format; link-port data transfer protocol; median filtering algorithm; noise reduction; real-time acquisition video image; video capture-output pre-processing system; video image storage space; video-capture-decode-encoding; Clocks; Decoding; Field programmable gate arrays; SDRAM; Streaming media; System-on-a-chip; FPGA; pre-processing; video capture; video output;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Ningbo

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067765

Filename

6067765