Low power area efficient dynamic quad PCM Codec with filter for communication applications

PCM Codec is a versatile device containing of both transmitter and receiver. Transmitter section consists of low pass filters, sampler, quantizer, encoder and the receiver consists of inverse quantizer, decoder, and low pass filters. 4th order filters are used for avoiding the noise in the signal. In this paper, 4 channels are used, only one channel is working at a time, during this period remaining 3 channels are in the off mode for avoiding the dynamic power dissipation. For implementing PCM Codec with filters we used Active HDL 5.1 for simulation and XILINX 8.1 for synthesis and the design is targeted to FPGA board. Finally we attained 85% of utilization on FPGA area. Each channel takes 16 bit input at the transmitter side, but at the receiver side only 14 bits are received accurately, remaining two bits received wrongly. So the accuracy is 87.5%. This problem is caused by the process of sampling and we solved it by decreasing the step size (Δ).