Large dynamic range high resolution digital delay generator based on FPGA

Author

Song, Yan ; Liang, Hao ; Zhou, Lei ; Du, Jiye ; Ma, Jiming ; Yue, Zhiqin

Author_Institution

Dept. of Modern Phys., State Key Lab. of Particle Detection & Electron., Univ. of Sci. & Technol. of China, Hefei, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

2116

Lastpage

2118

Abstract

A novel digital delay generator (DDG) based on FPGA was designed with 4.4ms range and 65ps resolution. The time-to- digital conversion (TDC) utilizing dual tapped delay lines was implemented in the FPGA to accurately measure the time interval between the rising edge of the FPGA global clock and the input trigger pulse. And the time interval was compensated in the following circuits by a AD9501 chip. The counter in the FPGA delays coarse time and another AD9501 chip delays fine time. To increase the accuracy, self-test block was developed in the FPGA to avoid the deviation induced from bad INL and DNL of AD9501 chips. Finally, the jitter of the system tested by TEK (TDS7404) oscilloscope was 400ps.

Keywords

delay circuits; field programmable gate arrays; oscilloscopes; FPGA; high resolution digital delay generator; input trigger pulse; large dynamic range; oscilloscope; time to digital conversion; Built-in self-test; Clocks; Delay; Delay lines; Field programmable gate arrays; Generators; Signal resolution; AD9501; Digital Delay Generator; FPGA; TDC;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Zhejiang

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067814

Filename

6067814