A low power hybrid clock gating technique for high frequency applications

Proliferation of high speed applications is leading towards increase in the dynamic power consumption per chip. Clock gating is found to be the most effective technique by which overall power consumptions can be reduced without sacrificing the performance and functionality of the chip. Look ahead clock gating is one of the new approaches in this area which overcomes the drawback of small time window of other conventional techniques. In this clock gating technique the main idea is to calculate the clock enable signal one cycle ahead of time, based on present cycle data of other flip-flops on which it depends. However there may be cases when this technique will block the output of logic block when they should be propagated to the output. Also another drawback of this technique is that it consumes more power. So in the proposed design the sequential and combinational blocks have been separated for overcoming the problem. Also lesser overhead of the gating circuitry has been used which leads to power reduction. In the proposed design three to four target flip-flops as well as source flip-flops have to be grouped for further power reduction. This paper has been implemented using Cadence Virtuoso with 90nm CMOS process technology and clock frequency of 0.1 GHz.