DocumentCode
2198692
Title
Test Efficiency Analysis and Improvement of SOC Test Platforms
Author
Hsieh, Tong-Yu ; Lee, Kuen-Jong ; You, Jian-Jhih
Author_Institution
Nat. Cheng Kung Univ., Tainan
fYear
2007
fDate
8-11 Oct. 2007
Firstpage
463
Lastpage
466
Abstract
Employing a test platform in an SOC design has been shown to be an effective method for SOC testing. However the test efficiency problem of a test platform has not been addressed. In this paper, we formally analyze the test efficiency of test platforms and seek for its optimization. We formulate the required numbers of test cycles for test platforms implemented with different test structures and/or executed with different test procedures. It is shown that up to 24X test time difference for platforms with different test structures/procedures is possible. Based on the derived formula, an appropriate test platform that can achieve best test efficiency with minimal area overhead can be determined.
Keywords
integrated circuit design; integrated circuit testing; system-on-chip; SOC test platform; system-on-chip; test efficiency analysis; Automatic testing; Built-in self-test; Costs; Design methodology; Hardware; Kernel; Signal generators; System testing; System-on-a-chip; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2007. ATS '07. 16th
Conference_Location
Beijing
ISSN
1081-7735
Print_ISBN
978-0-7695-2890-8
Type
conf
DOI
10.1109/ATS.2007.67
Filename
4388055
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