A tool-kit for the design and simulation of systolic algorithms

Since the development of VLSI technology, systolic arrays have become a good tool for solving real-time applications and problems with a high computational cost. The design of such schemes is a process that, if it can be done automatically, saves much time for the designer. Moreover, since a systolic array is implemented directly on hardware, it is clearly necessary to validate the design before its implementation. In this paper, we present a toolkit that can be used in several phases of the life-cycle of systolic algorithms. The toolkit consists of: an automatic design tool that automates P. Quinton´s (1984) design methodology, a parallel simulator of systolic algorithms that allows the validation of any design, and a graphic interface that makes the study of a simulation easier