Using FPGA configuration memory to accelerate yield learning for advanced process

The configuration memory is irregularly placed in a FPGA (Field Programmable Gate Array) chip and physically attached to the programmable logic circuits. This type of memory is more powerful than standard SRAM to monitor random or systematic process defects because the configuration memory test catches defects in both the memory cell and logic circuits. This paper will demonstrate a methodology of using this capability to accelerate yield learning for advanced process.