The layout implementations of high-speed low-power MCML cells

Author

Haiyan, Ni ; Jianping, Hu

Author_Institution

Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

2936

Lastpage

2939

Abstract

MOS Current-Mode Logic (MCML) is usually used for high-speed applications. In this paper, the design method of the low-power high-speed MOS MCML is addressed. The layout implementations of MCML basic gates are presented at a NCSU FreePDK 45 nm technology. The post-layout simulations are carried out. For normal supply voltage, the MCML basic gates can save more energy and have better performance than the traditional CMOS counterparts at 1GHz or higher operation frequencies. Scaling down the supply voltage of MCML circuits is investigated. The results show that the power consumption of MCML circuits can be reduced by lowering the supply voltage with a little performance degrading.

Keywords

MOS logic circuits; current-mode logic; integrated circuit layout; logic gates; low-power electronics; MCML basic gates; MOS current-mode logic; NCSU FreePDK technology; frequency 1 GHz; high-speed low-power MCML cells; layout implementations; normal supply voltage; power consumption; size 45 nm; CMOS integrated circuits; Integrated circuit modeling; Layout; Logic gates; Power demand; Power dissipation; Semiconductor device modeling; current-mode logic; high-speed applications; low-power; near-threshold operation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Zhejiang

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067866

Filename

6067866