Ground noise estimation and minimization in integrated circuit packages

A fast method for the estimation and minimization of ground noise in integrated circuit (IC) packages is desired. This method estimates and minimizes the shift away from the designed level (usually zero volts) in the reference potential of an IC. This shift is caused primarily by fast switching currents in the largely inductive IC package leads. The problem is addressed by combining a novel system matrix formulation which accounts for multiple ground circuits with pin assignment optimization by simulated annealing. By extraction of the parasitic self and mutual inductances from the tracks in a chip package one can construct a reduced system of linear equations which can then be used to solve for the estimated ground noise at any ground reference node in the package. This process is also appliable to packages with multiple separate grounds. With this capability, one can use the resulting ground noise values as the objective function for optimization by simulated annealing. The technique is expected to be sufficiently fast to be used in an interactive CAD (computer-aided design) environment