DocumentCode
2199476
Title
Sub-array Digital Multiple Beamfroming Technology on PowerPc+FPGA Architecture
Author
Qiu-Fei Yan ; Zhao-Yang Xu ; Zhao Yu
Author_Institution
723 Inst., CSIC, Yangzhou, China
Volume
2
fYear
2011
fDate
14-15 May 2011
Firstpage
420
Lastpage
425
Abstract
Phased array radar is very important in modern radar development, and sub-array digital multiple beam forming technology is the most significant technology in phased array radar. Digital multiple beam forming on each antenna element about large phased array radar is impossible because it needs so many A/D channels, sub-array digital multiple beam forming method can resolve this problem. This article mainly about, 1.Sub-array digital beam forming and low side lobe methods with radar work on search mode. 2.Sub-array digital beam forming (sum beam, azimuth difference beam, elevation difference beam) and low side lobe methods with radar work on tracking mode. 3. The function implementation of sub-array digital multiple beam forming with Power Pc+FPGA architecture. In this article, when radar work on different mode, there are different low side lobe weight Methods. When radar work on search mode, the low side lobe weight is on each antenna element controlled by digital attenuator embed in T/R module, and when radar work on tracking mode the low side lobe weight is on sub-array channel with digital style. The Power Pc+FPGA architecture used for radar signal processing is pioneer in China, experiment results prove that this architecture is better than other architectures, the whole processing time is less than 1 us.
Keywords
array signal processing; field programmable gate arrays; phased array radar; radar antennas; radar signal processing; radar tracking; A/D channels; T/R module; antenna element; digital attenuator; low sidelobe weight methods; phased array radar; powerPc-FPGA architecture; radar signal processing; radar tracking mode; subarray digital multiple beamforming technology; Array signal processing; Arrays; Radar antennas; Radar tracking; PowerPc+FPGA; RapidIO network; low side lobe; sub-array digital multiple beam;
fLanguage
English
Publisher
ieee
Conference_Titel
Network Computing and Information Security (NCIS), 2011 International Conference on
Conference_Location
Guilin
Print_ISBN
978-1-61284-347-6
Type
conf
DOI
10.1109/NCIS.2011.190
Filename
5948866
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