High-speed low-noise test system for IRFPA

According to the performance test requirements for the progress of IRFPA detector, a high performance DAQ system based on VXI and USB bus is designed and implemented. A variety of system ultra-low noise suppression measures effectively reduce the test system noise level, which has been proved by our preliminary test results. We use field programmable gate array (FPGA) to implement logic control. In the FPGA, the region of interest feature, online hardware compression algorithms and high-speed ping-pong transmission improve the flexibility and efficiency of the test. Through experiments on HgCdTe 640 × 512 (15 μm) IRFPA^[3], sampling rates is up to 40 MSPS and the background noise of test system is less than 115 uV with stable performance.