High-speed low-noise test system for IRFPA

Author

Wensong, Zhu ; Yonggang, Wang ; Dajun, Huang ; Lijun, Zhang ; Xiaoming, Lu ; Jun, Chen

Author_Institution

Dept. of Modern Phys., Univ. of Sci. & Technol. of China, Hefei, China

fYear

2011

fDate

9-11 Sept. 2011

Firstpage

1480

Lastpage

1484

Abstract

According to the performance test requirements for the progress of IRFPA detector, a high performance DAQ system based on VXI and USB bus is designed and implemented. A variety of system ultra-low noise suppression measures effectively reduce the test system noise level, which has been proved by our preliminary test results. We use field programmable gate array (FPGA) to implement logic control. In the FPGA, the region of interest feature, online hardware compression algorithms and high-speed ping-pong transmission improve the flexibility and efficiency of the test. Through experiments on HgCdTe 640 × 512 (15 μm) IRFPA^[3], sampling rates is up to 40 MSPS and the background noise of test system is less than 115 uV with stable performance.

Keywords

field programmable gate arrays; infrared detectors; infrared imaging; FPGA; IRFPA detector; USB bus; VXI bus; field programmable gate array; high-performance DAQ system; high-speed low-noise test system; high-speed ping-pong transmission; infrared focal plane array; logic control; online hardware compression algorithms; performance test requirements; test system noise level; ultralow-noise suppression measures; Clocks; Data acquisition; Detectors; Field programmable gate arrays; Generators; Noise measurement; Software; AD9244; IRFPA; hardware compression algorithms; high-speed low-noise; ping-pong transmission; test system;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Communications and Control (ICECC), 2011 International Conference on

Conference_Location

Zhejiang

Print_ISBN

978-1-4577-0320-1

Type

conf

DOI

10.1109/ICECC.2011.6067888

Filename

6067888