A 900-mV Area-Efficient Source-Degenerated CMOS Four-Quadrant Multiplier with 10.6-GHz Bandwidth

Author

Yuwono, Sigit ; Han, Sok-Kyun ; Lee, Sang-Gug

Author_Institution

Dept. of Inf. Commun. Eng., KAIST, Daejeon, South Korea

fYear

2009

fDate

24-26 Sept. 2009

Firstpage

1

Lastpage

4

Abstract

This paper presents a low-voltage area-efficient four-quadrant CMOS multiplier reconfigured in a source-degenerated topology and designed as a part of a correlator for an integrated ultra-wideband (UWB) transceiver. The simulation based on a 0.18-mum CMOS technology shows that the multiplier offers 10.6-GHz bandwidth while dissipating 290 muA from a 0.9-V supply.

Keywords

CMOS integrated circuits; analogue multipliers; correlators; low-power electronics; transceivers; ultra wideband communication; CMOS technology; UWB transceiver; analog multiplier; bandwidth 10.6 GHz; correlator; current 290 muA; low-voltage area-efficient four-quadrant CMOS multiplier; size 0.18 mum; source-degenerated topology; ultra-wideband transceiver; voltage 900 mV; Bandwidth; CMOS technology; Circuit topology; Correlators; Design engineering; Inductors; Radio frequency; Transceivers; Ultra wideband technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications, Networking and Mobile Computing, 2009. WiCom '09. 5th International Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-3692-7

Electronic_ISBN

978-1-4244-3693-4

Type

conf

DOI

10.1109/WICOM.2009.5305750

Filename

5305750