CORDIC implementation with parameterizable ASIC/SoC flow

Author

Zhenyu Qi ; Cabe, A.C. ; Jones, R.T. ; Stan, M.R.

Author_Institution

Charles L. Brown ECE Dept., Univ. of Virginia, Charlottesville, VA, USA

fYear

2010

fDate

18-21 March 2010

Firstpage

13

Lastpage

16

Abstract

A CORDIC processor with three computation modes is designed. The design targets low power applications. A novel fine grain clock gating scheme is employed to reduce power. The design is mapped to two technology nodes, i.e., 350 nm and 65 nm, using a script-based, parameterizable ASIC/SoC flow that can be easily adapted for different designs and technologies for fast concept-to-silicon mapping. Power numbers at both technology nodes are reported for the CORDIC design. The contribution of the paper includes both the actual design and the design flow.

Keywords

application specific integrated circuits; digital arithmetic; logic design; system-on-chip; CORDIC processor; application specific integrated circuits; concept-to-silicon mapping; coordinate rotation digital computer; parameterizable ASIC/SoC flow; size 350 nm; size 65 nm; system-on-chip; Application specific integrated circuits; Chirp; Clocks; Computer architecture; Discrete Fourier transforms; Discrete cosine transforms; Fast Fourier transforms; Fourier transforms; Hardware; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

IEEE SoutheastCon 2010 (SoutheastCon), Proceedings of the

Conference_Location

Concord, NC

Print_ISBN

978-1-4244-5854-7

Type

conf

DOI

10.1109/SECON.2010.5453930

Filename

5453930