FPGA-based Implementation of Efficient Sample Rate Conversion for Software Defined Radios

Software Radio is a burgeoning application in the domain of wireless communications. A lot of effort has recently been directed into developing practical algorithms for IF based, multi-standard Software Radio receiver architectures. Significant issues exist in developing an efficient implementation suitable for the processing of multiple standards through a single architecture with the help of sample rate conversion filters. In this context, this paper presents a practical implementation of multi-stage sample rate conversion in multi-standard software radios. This work includes complete design and subsequent implementation of sample rate conversion filters on a Xilinx Vertex II Pro FPGA Board. A high-level design methodology has been adopted that involves direct HDL code generation from algorithm description for testing and implementation on the FPGA. This approach is helpful in the rapid development and prototyping of multi-standard Software Radio and is facilitative in the initial stages of the design. The synthesized circuit utilizes 2% area of the Vertex II Pro FPGA. Power consumption reduction of around 2% is also visible in comparison to previously proposed reconfigurable decimation filter architecture.