Multiple threshold voltage for glitch power reduction

We address the problem of circuit-level design for low power. We describe a new method for glitch power reduction based on threshold voltage adjustment. The proposed method achieves both dynamic and leakage power reductions. We develop an optimization algorithm that optimizes the circuit netlist to achieve glitch energy reductions without affecting the overall circuit delay requirement. Applying the algorithm to C17 benchmark circuit implemented in a 65nm industrial Low Power CMOS process, we have achieved 14% total energy savings and 78% leakage energy savings at the expense of just 5% delay increase.