Interconnect topology for cell matrices based on low-power nanoscale devices

Novel devices based on carbon nanotube field effect transistors demonstrate lower power consumption over conventional CMOS technologies. In this paper, we focus on so-called matrix-based nanocomputer architectures that combine low power and routing overheads of cell matrices with flexibility of FPGAs. We introduce a new interconnect topology for cell matrices that provides the flexible logic depth and the ability to reconfigure cells and read their output values during data pipelining, with the following improvements: (+8%) mapping success rate, (~+50%) width of output data compared to the top results achieved by other topologies. Both improvements lead to the better matrix routability and, as a result, to the less area and power overheads of the whole matrix-based nanocomputer architecture. We present a thorough comparison to various prior interconnect topologies and demonstrate the trade-off between mapping success rate, time delay and wire length.